The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device that can reduce current consumption occurring in a data write path.
In general, when determining whether or not cells of a semiconductor memory device such as DRAM have a defect, testing all of the memory cells one-by-one requires a lot of time to individually test each cell as well as having a large cost associated with such a process.
Therefore, a general semiconductor memory device is developed to support a parallel test mode to reduce test time and cost. The parallel test mode determines a pass if all data is equally output in the read operation after writing the same data to multiple cells and determines a failure if any data is output differently. This process significantly reduces test time.
cells and determines a failure if any data is output differently. This process significantly reduces test time.
In the parallel test mode as mentioned, the data transfer is conventionally performed over a write path, which is a data transfer path in the write operation, as shown in FIG. 1.
Referring to FIG. 1, when in a normal mode, general data input to pads DQ0˜DQ3, respectively, are buffered via input buffers 10a˜10d and aligned in order of the burst sequence by a write data strobe signal WDQS via a data aligning unit 11a˜11d. 
The general aligned data ALGN_DATA0˜ALGN_DATA3 are amplified via input/output sense amplifying units 13a˜13d and transferred into corresponding memory cells through global input/output lines WGIO0˜WGIO3.
Meanwhile, the representative data input from a representative pad DQ0 among a plurality of pads DQ0˜DQ3 is aligned via the input buffer 10a and the data aligning unit 11a in the parallel test mode.
The representative data aligned by the data aligning unit 11a is routed into multiplexers 12b˜12d. The representative data ALGN_DATA0, which is aligned by the multiplexers 12b˜12d, is output to the input/output sense amplifying units 13a˜13d respectively when the parallel test signal PARA_TEST is enabled.
More specifically, only the representative data input from the representative pad DQ0 among the multiple pads DQ0˜DQ3, is used in order to write the same data to a plurality of memory cells in the parallel test mode.
As such, the prior art uses the multiplexers 12b˜12d controlled by the parallel test signal PARA_TEST in order to select and transfer only one of the data signals, e.g., ALGN_DATA0 and ALGN_DATA1, which are aligned in accordance with the normal mode and the parallel test mode.
However, unnecessary current consumption occurs during the transfer of the general aligned data ALGN_DATA0, since the general data ALGN_DATA0 that is aligned by the data aligning unit 11a is also routed into the multiplexers 12b˜12d in the write operation besides the parallel test mode.
Further, a semiconductor memory device, such as DDR2 SDRAM, generally includes an off-chip driver (OCD) controller 14 to control an impedance of a data output driver. To control the off-chip driver means to control an impedance of the data output driver at an optimal level in the present system by measuring voltage or current that flows in the data output driver of the memory device interfacing the data with external devices.
In order to control such an off-chip driver, a prior art semiconductor memory device is input with the representative data from the pad DQ0 for use in controlling the impedance of the data output driver in a standby mode (IDLE). A prior art semiconductor memory device also aligns the representative data via the data aligning unit 11a and then transfers the representative data to the off-chip driver controller 14. The off-chip driver controller 14 then outputs a signal OCD_OUT for use in controlling the impedance of the data output driver using the representative aligned data ALGN_DATA0.
However, unnecessary current consumption occurs during the transfer of the aligned data ALGN_DATA0 since the general data ALGN_DATA0 aligned via the data aligning unit 11a is routed into the off-chip driver controller 14 in the write operation besides the standby mode.
As such, since the general aligned data ALGN_DATA0 is also routed over other transfer paths in the write operation, the general aligned data ALGN_DATA0 is toggled unnecessarily leading to unnecessary current consumption. Such unnecessary current consumption results in increased operating burst write current (IDD4W) consumption of the semiconductor memory device.